As the technology nodes shrink in some integrated circuit (IC) designs, the spacing between hole vias and trenches continues to decrease. One process for etching hole vias and trenches into a dielectric layer is to place a photoresist over the surface of the dielectric layer and then etch the hole vias. The photoresist is removed and a second photoresist is placed over the etched dielectric layer and a second round of etching occurs to create either more hole vias or trenches. The twice etched dielectric layer is then subjected to wet stripping to remove the residual etchant materials and by-products of the etching process. To remove the wet stripping solution containing the residue and by-products from the dielectric layer, the assembly is rotated at high speed to cast off the solution.
However, the high speed rotation frequently causes the walls of the etched trenches to collapse. This line collapse phenomenon makes the collapsed trench unusable for metallization. Further, residual etchant and by-products remaining on the dielectric layer between the first and second etchings can prevent accurate creation of the desired features.
The use of dielectric materials having low dielectric constants of about 3.5 or less (i.e., low k dielectric materials) increases the above noted problems because of the low mechanical strength of low k dielectric materials. The purpose of a low k dielectric layer is to create lower parasitic capacitance between adjacent metal lines to provide faster circuit performance. The structural properties that cause the low k dielectrics to have the low parasitic capacitance also create the problem of low mechanical strength. Thus, as node size decreases the mechanical drawbacks of low k dielectric materials result in fewer usable connections within the dielectric layer.